Ultra-thin Body and Buried Oxide (BOX) devices (UTBB) are an attractive device structure in that they may allow for improved semiconductor device scaling. UTBB typically includes an ultra-thin Si body as a channel region, which is fully depleted and is beneficial for short channel effect (SCE) control. Also, with thinner BOX (about 25 nm or thinner), compared with ETSOI (extreme thin silicon-on-insulator) devices which have a thicker BOX (more than 50 nm), UTBB provides better scaling capability and the ability to tune threshold voltage (Vt) by applying reasonable back bias.
Shallow trench isolation (STI) regions are typically used in UTBB devices to electrically isolate the semiconductor devices (e.g., field effect transistors (FETs)) from one another. However, with the ultra-thin layers, typical processing operations may cause divots at the interface of the STI regions that can result in shorting from the device source/drain regions to the Si substrate.
Various approaches have generally been used for enhancing STI isolation structures. One such example is set forth in U.S. Pat. Pub. No. 2012/0119296 to Anderson et al., which is directed to trench-generated transistor structures wherein the source and drain of the transistor are defined by doped regions in the semiconductor material of the handle substrate of a semiconductor-on-insulator (SOI) wafer. The gate electrode may be defined from the semiconductor layer of the SOI wafer, which is separated from the handle wafer by an insulating layer.
Despite the existence of such configurations, further enhancements may be desirable for STI regions, particularly where relatively small dimensions are used, such as in UTBB devices.